1. Field of the Invention
The present invention relates to a driving circuit and a display comprising the same, and more particularly, it relates to a driving circuit supplying data to data lines and a display comprising the same.
2. Description of the Background Art
A driving circuit and a display supplying data to data lines are known in general. In relation to a display such as a liquid crystal display (LCD) or an organic EL (electroluminescence) display receiving a digital video signal, for example, a system converting the digital video signal to an analog video signal for writing the video signal (data) in a data line is known. In the specification, such a display is described with reference to a liquid crystal display (LCD).
Following recent demand for a miniature LCD employing polysilicon TFTs (thin film transistors), reduction of power consumption in a display system including an LCD panel and an external control IC and implementation of a digital interface corresponding to digitization of a peripheral device are highly required. In particular, digitization of a video signal is highly required. In order to digitize the video signal, a DAC (digital-to-analog converter) converting a digital video signal to an analog video signal must be built into the display panel. A liquid crystal display having such a built-in digital-to-analog converter is disclosed in Japanese Patent Laying-Open No. 7-261714 (1995) (first gazette) or Japanese Patent Laying-Open No. 2000-165243 (second gazette), for example.
FIG. 9 is a block diagram showing a liquid crystal display (LCD) according to first prior art disclosed in the aforementioned first gazette. Referring to FIG. 9, the liquid crystal display according to the first prior art comprises a horizontal scanning circuit 101, a vertical scanning circuit 102, a pixel part 103, a digital-to-analog conversion circuit 104 and switches 105. Each pixel forming the pixel part 103 includes a transistor 131, a capacitor 132 and a liquid crystal 133.
In schematic operation, the liquid crystal display according to the first prior art shown in FIG. 9 converts a digital video signal to an analog signal by the digital-to-analog conversion circuit 104, and thereafter directly drives each pixel selected through a horizontal address and a vertical address. This system, writing analog video data every pixel, is referred to as a dot sequential driving system.
However, a video data writing time in the dot sequential driving system depends on the cycle of a horizontal clock (CKH), and hence the video data must be written in a short time. Therefore, the liquid crystal display according to the first prior art shown in FIG. 9 requires high current drivability for the digital-to-analog conversion circuit 104. The current consumed by the digital-to-analog conversion circuit 104 having such high current drivability is disadvantageously increased.
The aforementioned second gazette discloses a liquid crystal display capable of reducing current drivability in a digital-to-analog conversion part by providing the digital-to-analog conversion part with an analog buffer while driving a single data line by the analog buffer and employing a line sequential driving system. FIG. 10 is a block diagram showing the liquid crystal display (LCD) according to second prior art disclosed in the second gazette. Referring to FIG. 10, the liquid crystal display according to the second prior art comprises an analog reference power source 201, a decoder 202, switches SW11, SW12, SW13, . . . , an output buffer (analog buffer) 203 and an analog buffer 204. The analog buffer 204, provided for adjusting an input potential for starting the output buffer 203, is driven with a power supply potential VDD2.
A switch SW1 is provided between the switches SW11 to SW18. A switch SW3 is provided between the analog buffer 204 and the output buffer 203. A parasitic capacitor C1 is connected to a first input terminal of the output buffer 203.
The decoder 202 selects a reference potential input in the output buffer 203 on the basis of digital video data D1, D2 and D3. The analog reference power source 201 resistively divides power supply potentials VDD1 and GND thereby generating the reference potential selected by the decoder 202.
The liquid crystal display according to the second prior art shown in FIG. 10 employs the line sequential driving system dissimilarly to the liquid crystal display according to the first prior art shown in FIG. 9. In the line sequential driving system, red, green or blue data for a single data line connected to a vertical scanning circuit is written in a high-level period of a write signal. The liquid crystal display according to the second prior art shown in FIG. 10 is provided with a single output buffer 203 every data line.
In the liquid crystal display according to the second prior art employing the line sequential driving system shown in FIG. 10, the output buffer (analog buffer) 203 drives a load corresponding to a single data line as described above, whereby currents consumed by the output buffer 203 and the analog buffer 204 can be reduced. Further, a sufficient write time can be ensured due to the line sequential driving system. Thus, precision of written data can also be improved.
However, the liquid crystal display according to the second prior art shown in FIG. 10 is provided with two analog buffers, i.e., the output buffer 203 and the analog buffer 204, every data line. Therefore, the number of the analog buffer circuits is increased in response to the number of the data lines. Thus, currents consumed by the analog buffer circuits are increased as a whole. In particular, through currents regularly flow in the analog buffer circuits in operation generally adjusting potentials to desired levels by current mirror circuits while consuming currents. Thus, current consumption tends to be increased.
Under such circumstances, the liquid crystal display according to the second prior art shown in FIG. 10 regularly operates the output buffer 203, disadvantageously leading to high current consumption. When a through current flows in the output buffer 203 provided every data line, current consumption is also disadvantageously increased.
In the liquid crystal display according to the second prior art shown in FIG. 10, further, the occupation areas of the output buffer 203 and the analog buffer 204 provided every data line are disadvantageously increased. Therefore, an area occupied by a part (frame part) other than a pixel part is increased in a display panel, to disadvantageously increase the area of a frame of the display.